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Musb2-phy �disabledwatchdog@ffd00200 !snps,dw-wdtF�� tw�,�@ �disabledwatchdog@ffd00300 !snps,dw-wdtF�� tx�,�A �disabledaliases_/soc/ethernet@ff800000i/soc/serial1@ffc02100q/soc/serial0@ffc02000y/soc/i2c@ffc02200~/soc/i2c@ffc02300memory@0:memoryF�chosen�serial1:115200n8 #address-cells#size-cellsmodelcompatibleenable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cellsclocksclock-namesresetsreset-namesfpga-mgr#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenaltr,sysmgr-sysconinterrupt-namesmac-addresssnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthsnps,axi-configstatusphy-modephy-addrmax-frame-sizephy-handletxd0-skew-pstxd1-skew-pstxd2-skew-pstxd3-skew-psrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiosgpio-line-namesnum-cstx-dma-channelrx-dma-channelcache-unifiedcache-levelprefetch-dataprefetch-instrarm,shared-overridecap-sd-highspeedbroken-cdbus-widthreg-namesaltr,sdr-sysconaltr,ecc-parentcdns,fifo-depthcdns,fifo-widthcdns,trigger-address#reset-cellsaltr,modrst-offsetcpu1-start-addrreg-shiftreg-io-width#phy-cellsphysphy-namesdr_modeethernet0serial1serial0i2c0i2c1stdout-path