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�auxclk0_ck�����.auxclk1_src_gate_ck@314z ti,composite-no-wait-gate-clock�auxclk1_src_gate_ck����auxclk1_src_mux_ck@314zti,composite-mux-clock�auxclk1_src_mux_ck ���� auxclk1_src_ckzti,composite-clock�auxclk1_src_ck� �!auxclk1_ck@314zti,divider-clock �auxclk1_ck�!����/auxclk2_src_gate_ck@318z ti,composite-no-wait-gate-clock�auxclk2_src_gate_ck����"auxclk2_src_mux_ck@318zti,composite-mux-clock�auxclk2_src_mux_ck ����#auxclk2_src_ckzti,composite-clock�auxclk2_src_ck�"#�$auxclk2_ck@318zti,divider-clock �auxclk2_ck�$����0auxclk3_src_gate_ck@31cz ti,composite-no-wait-gate-clock�auxclk3_src_gate_ck����%auxclk3_src_mux_ck@31czti,composite-mux-clock�auxclk3_src_mux_ck ����&auxclk3_src_ckzti,composite-clock�auxclk3_src_ck�%&�'auxclk3_ck@31czti,divider-clock �auxclk3_ck�'����1auxclk4_src_gate_ck@320z ti,composite-no-wait-gate-clock�auxclk4_src_gate_ck��� �(auxclk4_src_mux_ck@320zti,composite-mux-clock�auxclk4_src_mux_ck ��� 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[@wdt@0ti,omap4-wdtti,omap3-wdt�� BPtarget-module@8000ti,sysc-omap2-timerti,sysc����brevsyscsyss ' l � �fck+ [�Sgtimer@0ti,omap3430-timer��� �fcktimer_sys_ck B%r � �target-module@c000ti,sysc-omap2ti,sysc����brevsyscsyss ' l � X�fck+ [�keypad@0ti,omap4-keypad�� Bxbmputarget-module@e000ti,sysc-omap4ti,sysc��� brevsyscl+ [�pinmux@40 ti,omap4-padconfpinctrl-single�@8+����pinmux_twl6030_wkup_pins��ssegment@20000simple-pm-bus+�[``��  00@@PPpp����target-module@0ti,sysc disabled+ [target-module@2000ti,sysc disabled+ [ target-module@4000ti,sysc disabled+ [@target-module@6000ti,sysc disabled+0[`p �0�interconnect@4a000000ti,omap4-l4-cfgsimple-pm-busM4 �5�fck�JJJ baplaia0+T[JJJJ J (J(0J0segment@0simple-pm-bus+�[ 00@@PP``pp����@  00�� ��``pp�� @@PPtarget-module@2000ti,sysc-omap4ti,sysc�   brevsyscl+ [ scm@0ti,omap4-scm-coresimple-bus�+ [scm_conf@0syscon�+��control-phy@300ti,control-phy-usb2�bpower�gcontrol-phy@33cti,control-phy-otghs�<botghs_control�etarget-module@4000ti,sysc-omap4ti,sysc�@brev+ [@cm1@0ti,omap4-cm1simple-bus� + [ clocks+extalt_clkin_ckz fixed-clock�extalt_clkin_ck �D�pad_clks_src_ckz fixed-clock�pad_clks_src_ck ��6pad_clks_ck@108zti,gate-clock �pad_clks_ck�6��pad_slimbus_core_clks_ckz fixed-clock�pad_slimbus_core_clks_ck �secure_32k_clk_src_ckz fixed-clock�secure_32k_clk_src_ck �slimbus_src_clkz fixed-clock�slimbus_src_clk ��7slimbus_clk@108zti,gate-clock �slimbus_clk�7� �sys_32k_ckz fixed-clock �sys_32k_ck ��virt_12000000_ckz fixed-clock�virt_12000000_ck �� virt_13000000_ckz fixed-clock�virt_13000000_ck �]@� virt_16800000_ckz fixed-clock�virt_16800000_ck Y�virt_19200000_ckz fixed-clock�virt_19200000_ck $��virt_26000000_ckz fixed-clock�virt_26000000_ck ����virt_27000000_ckz fixed-clock�virt_27000000_ck ����virt_38400000_ckz fixed-clock�virt_38400000_ck I��tie_low_clock_ckz fixed-clock�tie_low_clock_ck utmi_phy_clkout_ckz fixed-clock�utmi_phy_clkout_ck ��xclk60mhsp1_ckz fixed-clock�xclk60mhsp1_ck ���`xclk60mhsp2_ckz fixed-clock�xclk60mhsp2_ck ���axclk60motg_ckz fixed-clock�xclk60motg_ck ��dpll_abe_ck@1e0zti,omap4-dpll-m4xen-clock �dpll_abe_ck�89������:dpll_abe_x2_ck@1f0zti,omap4-dpll-x2-clock�dpll_abe_x2_ck�:���;dpll_abe_m2x2_ck@1f0zti,divider-clock�dpll_abe_m2x2_ck�;����/�<abe_24m_fclkzfixed-factor-clock �abe_24m_fclk�<��abe_clk@108zti,divider-clock�abe_clk�<��Fdpll_abe_m3x2_ck@1f4zti,divider-clock�dpll_abe_m3x2_ck�;����/�=core_hsd_byp_clk_mux_ck@12cz ti,mux-clock�core_hsd_byp_clk_mux_ck�=��,�>dpll_core_ck@120zti,omap4-dpll-core-clock �dpll_core_ck�>� $,(�?dpll_core_x2_ckzti,omap4-dpll-x2-clock�dpll_core_x2_ck�?�@dpll_core_m6x2_ck@140zti,divider-clock�dpll_core_m6x2_ck�@��@�/dpll_core_m2_ck@130zti,divider-clock�dpll_core_m2_ck�?��0�/�Addrphy_ckzfixed-factor-clock �ddrphy_ck�A��dpll_core_m5x2_ck@13czti,divider-clock�dpll_core_m5x2_ck�@��<�/�Bdiv_core_ck@100zti,divider-clock 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�dpll_mpu_ck�L�`dlh�dpll_mpu_m2_ck@170zti,divider-clock�dpll_mpu_m2_ck���p�/per_hs_clk_div_ckzfixed-factor-clock�per_hs_clk_div_ck�=���Qusb_hs_clk_div_ckzfixed-factor-clock�usb_hs_clk_div_ck�=���Wl3_div_ck@100zti,divider-clock �l3_div_ck�M����Nl4_div_ck@100zti,divider-clock �l4_div_ck�N���lp_clk_div_ckzfixed-factor-clock�lp_clk_div_ck�<���mpu_periphclkzfixed-factor-clock�mpu_periphclk����ocp_abe_iclk@528zti,divider-clock �ocp_abe_iclk �O��(�per_abe_24m_fclkzfixed-factor-clock�per_abe_24m_fclk�P��dummy_ckz fixed-clock �dummy_ck clockdomainsmpuss_cm@300 ti,omap4-cm �mpuss_cm�+ [clk@20 ti,clkctrl�mpuss_clkctrl� z�}tesla_cm@400 ti,omap4-cm �tesla_cm�+ [clk@20 ti,clkctrl�tesla_clkctrl� z�babe_cm@500 ti,omap4-cm�abe_cm�+ [clk@20 ti,clkctrl �abe_clkctrl� lz�Otarget-module@8000ti,sysc-omap4ti,sysc��brev+ [� cm2@0ti,omap4-cm2simple-bus� + [ clocks+per_hsd_byp_clk_mux_ck@14cz ti,mux-clock�per_hsd_byp_clk_mux_ck�Q��L�Rdpll_per_ck@140zti,omap4-dpll-clock �dpll_per_ck�R�@DLH�Sdpll_per_m2_ck@150zti,divider-clock�dpll_per_m2_ck�S��P��[dpll_per_x2_ck@150zti,omap4-dpll-x2-clock�dpll_per_x2_ck�S�P�Tdpll_per_m2x2_ck@150zti,divider-clock�dpll_per_m2x2_ck�T��P�/�Zdpll_per_m3x2_gate_ck@154z ti,composite-no-wait-gate-clock�dpll_per_m3x2_gate_ck�T��T�Udpll_per_m3x2_div_ck@154zti,composite-divider-clock�dpll_per_m3x2_div_ck�T��T��Vdpll_per_m3x2_ckzti,composite-clock�dpll_per_m3x2_ck�UV�dpll_per_m4x2_ck@158zti,divider-clock�dpll_per_m4x2_ck�T��X�/�dpll_per_m5x2_ck@15czti,divider-clock�dpll_per_m5x2_ck�T��\�/dpll_per_m6x2_ck@160zti,divider-clock�dpll_per_m6x2_ck�T��`�/�Ydpll_per_m7x2_ck@164zti,divider-clock�dpll_per_m7x2_ck�T��d�/��dpll_usb_ck@180zti,omap4-dpll-j-type-clock �dpll_usb_ck�W������Xdpll_usb_clkdcoldo_ck@1b4zti,fixed-factor-clock�dpll_usb_clkdcoldo_ck�Xq��~/dpll_usb_m2_ck@190zti,divider-clock�dpll_usb_m2_ck�X����/�\ducati_clk_mux_ck@100z ti,mux-clock�ducati_clk_mux_ck�MY�func_12m_fclkzfixed-factor-clock�func_12m_fclk�Z��func_24m_clkzfixed-factor-clock �func_24m_clk�[��func_24mc_fclkzfixed-factor-clock�func_24mc_fclk�Z��func_48m_fclk@108zti,divider-clock�func_48m_fclk�Z��func_48mc_fclkzfixed-factor-clock�func_48mc_fclk�Z��func_64m_fclk@108zti,divider-clock�func_64m_fclk���func_96m_fclk@108zti,divider-clock�func_96m_fclk�Z��init_60m_fclk@104zti,divider-clock�init_60m_fclk�\���_per_abe_nc_fclk@108zti,divider-clock�per_abe_nc_fclk�P��usb_phy_cm_clk32k@640zti,gate-clock�usb_phy_cm_clk32k���@�hclockdomainsl3_init_clkdmti,clockdomain�l3_init_clkdm�Xl4_ao_cm@600 ti,omap4-cm �l4_ao_cm�+ [clk@20 ti,clkctrl�l4_ao_clkctrl� z�jl3_1_cm@700 ti,omap4-cm�l3_1_cm�+ [clk@20 ti,clkctrl �l3_1_clkctrl� z�l3_2_cm@800 ti,omap4-cm�l3_2_cm�+ [clk@20 ti,clkctrl �l3_2_clkctrl� z�ducati_cm@900 ti,omap4-cm �ducati_cm� + [ clk@20 ti,clkctrl�ducati_clkctrl� z��l3_dma_cm@a00 ti,omap4-cm �l3_dma_cm� + [ clk@20 ti,clkctrl�l3_dma_clkctrl� z�]l3_emif_cm@b00 ti,omap4-cm �l3_emif_cm� + [ clk@20 ti,clkctrl�l3_emif_clkctrl� z��d2d_cm@c00 ti,omap4-cm�d2d_cm� + [ clk@20 ti,clkctrl �d2d_clkctrl� z�il4_cfg_cm@d00 ti,omap4-cm �l4_cfg_cm� + [ clk@20 ti,clkctrl�l4_cfg_clkctrl� z�5l3_instr_cm@e00 ti,omap4-cm �l3_instr_cm�+ [clk@20 ti,clkctrl�l3_instr_clkctrl� $z� ivahd_cm@f00 ti,omap4-cm �ivahd_cm�+ [clk@20 ti,clkctrl�ivahd_clkctrl� z��iss_cm@1000 ti,omap4-cm�iss_cm�+ [clk@20 ti,clkctrl �iss_clkctrl� z�ll3_dss_cm@1100 ti,omap4-cm �l3_dss_cm�+ [clk@20 ti,clkctrl�l3_dss_clkctrl� z��l3_gfx_cm@1200 ti,omap4-cm �l3_gfx_cm�+ [clk@20 ti,clkctrl�l3_gfx_clkctrl� z��l3_init_cm@1300 ti,omap4-cm �l3_init_cm�+ [clk@20 ti,clkctrl�l3_init_clkctrl� �z�^clock@1400 ti,omap4-cm �l4_per_cm�+ [clock@20 ti,clkctrl�l4_per_clkctrl� Dz�mclock@1a0 ti,clkctrl�l4_secure_clkctrl��<z�vtarget-module@56000ti,sysc-omap2ti,sysc�``,`(brevsyscsyss # � l �]�fck+ [`dma-controller@0ti,omap4430-sdmati,omap-sdma�0B  �� ��wtarget-module@58000ti,sysc-omap2ti,sysc����brevsyscsyss #�l �^�fck+ [�Phsi@0 ti,omap4-hsi�@Pbsysgdd �^�hsi_fck BG�gdd_mpu+ [@hsi-port@2000ti,omap4-hsi-port� (btxrx BChsi-port@3000ti,omap4-hsi-port�08btxrx BDtarget-module@5e000ti,sysc disabled+ [� target-module@62000ti,sysc-omap2ti,sysc�   brevsyscsyss  l �^H�fck+ [ usbhstll@0 ti,usbhs-tll� BNtarget-module@64000ti,sysc-omap4ti,sysc�@@@brevsyscsyss �l �^8�fck+ [@usbhshost@0ti,usbhs-host�+ [ �_`a3�refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2ohci@800ti,ohci-omap3� BL�ehci@c00 ti,ehci-omap�  BMtarget-module@66000ti,sysc-omap2ti,sysc�```brevsyscsyss  l �b�fckMc�c�rstctrl+ [`mmu@0ti,omap4-iommu� B���segment@80000simple-pm-bus+[� �� �� �� �� �� �@@PP``pp` `p p� �� �� �� �� �� �� �� �target-module@29000ti,sysc disabled+ [�target-module@2b000ti,sysc-omap2ti,sysc����brevsyscsyss  �l �^@�fck+ [�usb_otg_hs@0ti,omap4-musb��B\]�mcdmadd usb2-phy)1 :eFdefaultTf^mr2target-module@2d000ti,sysc-omap2ti,sysc����brevsyscsyss  l �^��fck+ [�ocp2scp@0ti,omap-ocp2scp�+ [usb2phy@80 ti,omap-usb2��X:g�h�wkupclkx�dtarget-module@36000ti,sysc-omap2ti,sysc�```brevsyscsyss l �i�fck+ [`target-module@4d000ti,sysc-omap2ti,sysc����brevsyscsyss l �i�fck+ [�target-module@59000ti,sysc-omap4-srti,sysc��8bsysc l �j�fck+ [�smartreflex@0ti,omap4-smartreflex-mpu�� Btarget-module@5b000ti,sysc-omap4-srti,sysc��8bsysc l �j�fck+ [�smartreflex@0ti,omap4-smartreflex-iva�� Bftarget-module@5d000ti,sysc-omap4-srti,sysc��8bsysc l �j�fck+ [�smartreflex@0ti,omap4-smartreflex-core�� Btarget-module@60000ti,sysc disabled+ [target-module@74000ti,sysc-omap4ti,sysc�@@ brevsysc  l �5�fck+ [@mailbox@0ti,omap4-mailbox� B�����mbox-ipu � ���mbox-dsp � ���target-module@76000ti,sysc-omap2ti,sysc�```brevsyscsyss  l �5�fck+ [`spinlock@0ti,omap4-hwspinlock��segment@100000simple-pm-bus+`[  00��������target-module@0ti,sysc-omap4ti,sysc� brevsyscl+ [pinmux@40 ti,omap4-padconfpinctrl-single�@�+����Fdefault�opinmux_uart3_pins��npinmux_i2c1_pins����qpinmux_i2c2_pins����upinmux_i2c3_pins����ppinmux_i2c4_pins����{pinmux_mmc2_pinsP�  BD�ypinmux_usb_otg_hs_pins�TVX�fpinmux_twl6030_pins�^A�romap4_padconf_global@5a0sysconsimple-bus��p+ [�p�kpbias_regulator@60ti,pbias-omap4ti,pbias-omap�`�kpbias_mmc_omap4�pbias_mmc_omap4�w@-���xtarget-module@2000ti,sysc disabled+ [ target-module@8000ti,sysc disabled+ [�target-module@a000ti,sysc-omap4ti,sysc��� brevsysc  � l �l�fck+ [�segment@180000simple-pm-bus+segment@200000simple-pm-bus+h[�!��!�� �� �@ @P P` `p p ! 0!0� �� �!!`!`p!p@!@P!P�!��!�""`"`p"p�"��"��"��"��!��!�target-module@4000ti,sysc disabled+ [@target-module@6000ti,sysc disabled+ [`target-module@a000ti,sysc disabled+ [�target-module@c000ti,sysc disabled+ [�target-module@10000ti,sysc disabled+ [target-module@12000ti,sysc disabled+ [ target-module@14000ti,sysc disabled+ [@target-module@16000ti,sysc disabled+ [`target-module@18000ti,sysc disabled+ [�target-module@1c000ti,sysc disabled+ [�target-module@1e000ti,sysc disabled+ [�target-module@20000ti,sysc disabled+ [target-module@26000ti,sysc disabled+ [`target-module@28000ti,sysc disabled+ [�target-module@2a000ti,sysc disabled+ [�segment@280000simple-pm-bus+segment@300000simple-pm-bus+�[042@@2@ `2`p2p�2��2�3�2� �2�@target-module@0ti,sysc disabled+x[@@@ ``pp������ ��@interconnect@48000000ti,omap4-l4-persimple-pm-busM �m��fck0�HHHHHHbaplaia0ia1ia2ia3+[H H segment@0simple-pm-bus+�[  00@@PP``pp����PP``pp��������������������������  00 ` ` p p``pp����``pp����    � � � � � � � � � � � � � � � �  @ @ ` ` � �@ � � � � � �  0 0 @ @ P P � � � � � � � �    P P ` `  0 0 P Ptarget-module@20000ti,sysc-omap2ti,sysc�PTXbrevsyscsyss l �m0�fck+ [serial@0ti,omap4-uart� BJ �lFdefaultTn.Jotarget-module@32000ti,sysc-omap2-timerti,sysc�   brevsyscsyss ' l �m�fck+ [ timer@0ti,omap3430-timer���m�fcktimer_sys_ck B&target-module@34000ti,sysc-omap4-timerti,sysc�@@ brevsysc l �m �fck+ [@timer@0ti,omap4430-timer���m �fcktimer_sys_ck B'target-module@36000ti,sysc-omap4-timerti,sysc�`` brevsysc l �m(�fck+ [`timer@0ti,omap4430-timer���m(�fcktimer_sys_ck B(target-module@3e000ti,sysc-omap4-timerti,sysc��� brevsysc l �m0�fck+ [�timer@0ti,omap4430-timer���m0�fcktimer_sys_ck B-Btarget-module@40000ti,sysc disabled+ [target-module@55000ti,sysc-omap2ti,sysc�PPQbrevsyscsyss l�m@m@ �fckdbclk+ [Pgpio@0ti,omap4-gpio� B7Gtarget-module@57000ti,sysc-omap2ti,sysc�ppqbrevsyscsyss l�mHmH �fckdbclk+ [pgpio@0ti,omap4-gpio� B7G��target-module@59000ti,sysc-omap2ti,sysc����brevsyscsyss l�mPmP �fckdbclk+ [�gpio@0ti,omap4-gpio� B 7Gtarget-module@5b000ti,sysc-omap2ti,sysc����brevsyscsyss l�mXmX �fckdbclk+ [�gpio@0ti,omap4-gpio� B!7Gtarget-module@5d000ti,sysc-omap2ti,sysc����brevsyscsyss l�m`m` �fckdbclk+ [�gpio@0ti,omap4-gpio� B"7Gtarget-module@60000ti,sysc-omap2ti,sysc��brevsyscsyss l �m��fck+ [i2c@0 ti,omap4-i2c� B=+FdefaultTp �target-module@6a000ti,sysc-omap2ti,sysc��P�T�Xbrevsyscsyss l �m �fck+ [�serial@0ti,omap4-uart� BH �ltarget-module@6c000ti,sysc-omap2ti,sysc��P�T�Xbrevsyscsyss l �m(�fck+ [�serial@0ti,omap4-uart� BI �ltarget-module@6e000ti,sysc-omap2ti,sysc��P�T�Xbrevsyscsyss l �m8�fck+ [�serial@0ti,omap4-uart� BF �ltarget-module@70000ti,sysc-omap2ti,sysc��brevsyscsyss l �m��fck+ [i2c@0 ti,omap4-i2c� B8+FdefaultTq �twl@48�H B ti,twl6030FdefaultTrspowerti,twl6030-powerOrtcti,twl4030-rtcB regulator-vaux1ti,twl6030-vaux1�B@-���zregulator-vaux2ti,twl6030-vaux2�O�*��regulator-vaux3ti,twl6030-vaux3�B@-��regulator-vmmcti,twl6030-vmmc�O�-��regulator-vppti,twl6030-vpp�w@&%�regulator-vusimti,twl6030-vusim�O�,@ regulator-vdacti,twl6030-vdacregulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxiojregulator-vusbti,twl6030-vusb�tregulator-v1v8ti,twl6030-v1v8jregulator-v2v1ti,twl6030-v2v1jusb-comparatorti,twl6030-usbB ~tpwmti,twl6030-pwm���pwmledti,twl6030-pwmled�gpadcti,twl6030-gpadcB�target-module@72000ti,sysc-omap2ti,sysc�   �brevsyscsyss l �m��fck+ [ i2c@0 ti,omap4-i2c� B9+FdefaultTu �target-module@76000ti,sysc-omap4ti,sysc�`` brevsysc l �m�fck+ [`target-module@78000ti,sysc-omap2ti,sysc����brevsyscsyss  l �m8�fck+ [�elm@0ti,am3352-elm�  B disabledtarget-module@86000ti,sysc-omap2-timerti,sysc�```brevsyscsyss ' l �m�fck+ [`timer@0ti,omap3430-timer���m�fcktimer_sys_ck B.Btarget-module@88000ti,sysc-omap4-timerti,sysc��� brevsysc l �m�fck+ [�timer@0ti,omap4430-timer���m�fcktimer_sys_ck B/Btarget-module@90000ti,sysc-omap2ti,sysc� � � brevsysc l �v �fck+ [ rng@0 ti,omap4-rng�  B4target-module@96000ti,sysc-omap2ti,sysc� `�bsysc  l �m��fck+ [ `mcbsp@0ti,omap4-mcbsp��bmpu B�common���ww �txrx disabledtarget-module@98000ti,sysc-omap4ti,sysc� � � brevsysc l �m��fck+ [ �spi@0ti,omap4-mcspi� BA+�@�w#w$w%w&w'w(w)w* �tx0rx0tx1rx1tx2rx2tx3rx3target-module@9a000ti,sysc-omap4ti,sysc� � � brevsysc l �m��fck+ [ �spi@0ti,omap4-mcspi� BB+� �w+w,w-w.�tx0rx0tx1rx1target-module@9c000ti,sysc-omap4ti,sysc� � � brevsysc �l �^�fck+ [ �mmc@0ti,omap4-hsmmc� BS���w=w>�txrx�x disabledtarget-module@9e000ti,sysc disabled+ [ �target-module@a2000ti,sysc disabled+ [ target-module@a4000ti,sysc disabled+[ @ Ptarget-module@a5000ti,sysc-omap2ti,sysc� P0 P4 P8brevsyscsyss l �v�fck+ [ Pdes@0 ti,omap4-des�� BR�wuwt�txrxtarget-module@a8000ti,sysc disabled+ [ �@target-module@ad000ti,sysc-omap4ti,sysc� � � brevsysc �l �m�fck+ [ �mmc@0ti,omap4-hsmmc� B^��wMwN�txrx disabledtarget-module@b0000ti,sysc disabled+ [ target-module@b2000ti,sysc-omap2ti,sysc�   brevsyscsyss S �mh�fck+ [ 1w@0 ti,omap3-1w� B:target-module@b4000ti,sysc-omap4ti,sysc� @ @ brevsysc �l �^�fck+ [ @mmc@0ti,omap4-hsmmc� BV��w/w0�txrxFdefaultTyz target-module@b8000ti,sysc-omap4ti,sysc� � � brevsysc l �m��fck+ [ �spi@0ti,omap4-mcspi� B[+��ww�tx0rx0target-module@ba000ti,sysc-omap4ti,sysc� � � brevsysc l �m��fck+ [ �spi@0ti,omap4-mcspi� B0+��wFwG�tx0rx0target-module@d1000ti,sysc-omap4ti,sysc�   brevsysc �l �m�fck+ [ mmc@0ti,omap4-hsmmc� B`��w9w:�txrx disabledtarget-module@d5000ti,sysc-omap4ti,sysc� P P brevsysc �l �m@�fck+ [ Pmmc@0ti,omap4-hsmmc� B;��w;w<�txrxsegment@200000simple-pm-bus+[55target-module@150000ti,sysc-omap2ti,sysc��brevsyscsyss l �m��fck+ [i2c@0 ti,omap4-i2c� B>+FdefaultT{ �target-module@48210000ti,sysc-omap4-simpleti,syscM| �}�fck+ [H!mpu ti,omap4-mpu*~interconnect@40100000ti,omap4-l4-abesimple-pm-bus�@@blaapM+[@IIsegment@0simple-pm-bus+0[  00@@PP``pp������������  00����������������      IIIII I I0I0I@I@IPIPI`I`IpIpI�I�I�I�I�I�I�I�I�I�I�I�IIIII I I0I0I�I�I�I�I�I�I�I�I�I�I�I�I�I�I�I�IIIII I I I I I I I III I target-module@22000ti,sysc-omap2ti,sysc� �bsysc  l �O(�fck+[ I I mcbsp@0ti,omap4-mcbsp��I �bmpudma B�common���w!w"�txrx disabledtarget-module@24000ti,sysc-omap2ti,sysc�@�bsysc  l �O0�fck+[@I@I@mcbsp@0ti,omap4-mcbsp��I@�bmpudma B�common���ww�txrx disabledtarget-module@26000ti,sysc-omap2ti,sysc�`�bsysc  l �O8�fck+[`I`I`mcbsp@0ti,omap4-mcbsp��I`�bmpudma B�common���ww�txrx disabledtarget-module@28000ti,sysc-mcaspti,sysc��� brevsysc l �O �fck+0[�I�I� �I�I�mcasp@0ti,omap4-mcasp-audio� I�bmpudat Bm�tx�w�tx �O �fck/7 disabledtarget-module@2e000ti,sysc-omap4ti,sysc��� brevsysc l �O�fck+[�I�I�dmic@0ti,omap4-dmic�I�bmpudma Br�wC�up_link disabledtarget-module@30000ti,sysc-omap2ti,sysc�brevsyscsyss "l �Oh�fck+[IIwdt@0ti,omap4-wdtti,omap3-wdt�� BPtarget-module@32000ti,sysc-omap4ti,sysc�   brevsysc l �O�fck+[ I I  disabledmcpdm@0ti,omap4-mcpdm�I bmpudma Bp�wAwB�up_linkdn_linktarget-module@38000ti,sysc-omap4-timerti,sysc��� brevsysc l �OH�fck+[�I�I�timer@0ti,omap4430-timer��I���OH��fcktimer_sys_ck B)Btarget-module@3a000ti,sysc-omap4-timerti,sysc��� brevsysc l �OP�fck+[�I�I�timer@0ti,omap4430-timer��I���OP��fcktimer_sys_ck B*Btarget-module@3c000ti,sysc-omap4-timerti,sysc��� brevsysc l �OX�fck+[�I�I�timer@0ti,omap4430-timer��I���OX��fcktimer_sys_ck B+Btarget-module@3e000ti,sysc-omap4-timerti,sysc��� brevsysc l �O`�fck+[�I�I�timer@0ti,omap4430-timer��I���O`��fcktimer_sys_ck B,BBtarget-module@80000ti,sysc disabled+[IItarget-module@a0000ti,sysc disabled+[ I I target-module@c0000ti,sysc disabled+[ I I target-module@f1000ti,sysc-omap4ti,sysc� brevsysc� l �O�fck+[IItarget-module@50000000ti,sysc-omap2ti,sysc�PPPbrevsyscsyss lO ��fck+[PP@gpmc@50000000ti,omap4430-gpmc�P+ B�w�rxtxbn�N�fck7Gtarget-module@52000000ti,sysc-omap4ti,sysc�RR brevsysc �lM� �l�fck+ [Rtarget-module@54000000ti,sysc-omap4-simpleti,syscM� ��fck+ [Tpmuarm,cortex-a9-pmutarget-module@55082000ti,sysc-omap2ti,sysc�U U U brevsyscsyss l  ���fck�4�rstctrl [U +mmu@0ti,omap4-iommu� Bd����target-module@4012c000ti,sysc-omap4ti,sysc�@�@� brevsysc l �O@�fck+[@�I�I�target-module@4e000000ti,sysc-omap2ti,sysc�NN brevsysc l [N+dmm@0 ti,omap4-dmm� Bqtarget-module@4c000000ti,sysc-omap4-simpleti,sysc�Lbrev ���fckg+ [Lemif@0 ti,emif-4d� Bn����target-module@4d000000ti,sysc-omap4-simpleti,sysc�Mbrev ���fckg+ [Memif@0 ti,emif-4d� Bo����dsp ti,omap4-dsp �����c �b�omap4-dsp-fw.xe64T��� disabledipu@55020000 ti,omap4-ipu�Ubl2ram���44 ���omap4-ipu-fw.xem3��� disabledtarget-module@4b501000ti,sysc-omap2ti,sysc�KP�KP�KP�brevsyscsyss l �v�fck+ [KPaes@0 ti,omap4-aes�� BU�wown�txrxtarget-module@4b701000ti,sysc-omap2ti,sysc�Kp�Kp�Kp�brevsyscsyss l �v�fck+ [Kpaes@0 ti,omap4-aes�� B@�wrwq�txrxtarget-module@4b100000ti,sysc-omap3-shamti,sysc�KKKbrevsyscsyss  l �v(�fck+ [Ksham@0ti,omap4-sham� B3�ww�rxregulator-abb-mpu ti,abb-v2�abb_mpu+��2/okay�J0{�J0`bbase-addressint-addressx?��O���1�regulator-abb-iva ti,abb-v2�abb_iva+��2/ disabled�J0{�J0`bbase-addressint-addresstarget-module@56000000ti,sysc-omap4ti,sysc�V�V� brevsysc�lM� ���fck+ [V���\O���target-module@58000000ti,sysc-omap2ti,sysc�XX brevsyssM�0��� � � �fckhdmi_clksys_clktv_clk+ [Xdss@0 ti,omap4-dss�� disabled ���fck+ [target-module@1000ti,sysc-omap2ti,sysc�brevsyscsyss l � ���  �fcksys_clk+ [dispc@0ti,omap4-dispc� B ���fcktarget-module@2000ti,sysc-omap2ti,sysc�   brevsyscsyss l ���  �fcksys_clk+ [ encoder@0� disabled��N�fckicktarget-module@3000ti,sysc-omap2ti,sysc�0brev �� �sys_clk+ [0encoder@0ti,omap4-venc� disabled �� �fcktarget-module@4000ti,sysc-omap2ti,sysc�@@@brevsyscsyss l + [@encoder@0 ti,omap4-dsi�@ bprotophypll B5 disabled���  �fcksys_clk+target-module@5000ti,sysc-omap2ti,sysc�PPPbrevsyscsyss l + [Pencoder@0 ti,omap4-dsi�@ bprotophypll BT disabled���  �fcksys_clk+target-module@6000ti,sysc-omap4ti,sysc�`` brevsyscl �� � �fckdss_clk+ [` encoder@0ti,omap4-hdmi �bwppllphycore Be disabled�� �  �fcksys_clk�wL �audio_txtarget-module@5a000000ti,sysc-omap4ti,sysc�Z�Z� brevsysc � lM����rstctrl ���fck+[ZZ[[iva ti,ivahdbandgap@4a002260�J"`J#,ti,omap4430-bandgap K�Q��thermal-zonescpu_thermalg�}����N tripscpu_alert������passive��cpu_crit��H�� �criticalcooling-mapsmap0�� ����������memory@80000000�memory�� led-controller pwm-ledsled-1�green ��w5��led-2�orange ��w5�� compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3mmc0mmc1mmc2mmc3mmc4serial0serial1serial2serial3rproc0rproc1device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-points#cooling-cellsphandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptspower-domainsrangesreg-namesti,sysc-sidle#clock-cellsclock-output-namesti,index-starts-at-oneti,bit-shiftclock-multclock-divti,max-divti,dividers#power-domain-cells#reset-cellsti,sysc-maskti,syss-maskti,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parents#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsstatusclock-frequencyti,autoidle-shiftti,invert-autoidle-bitti,index-power-of-twoassigned-clock-ratesti,clock-divti,clock-multti,sysc-midle#dma-cellsdma-channelsdma-requestsinterrupt-namesremote-wakeup-connectedresetsreset-names#iommu-cellsusb-phyphysphy-namesmultipointnum-epsram-bitsctrl-modulepinctrl-namespinctrl-0interface-typemodepower#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rx#hwlock-cellssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,sysc-delay-usinterrupts-extendedti,timer-pwmti,system-power-controllerregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,buffer-sizedmasdma-namesti,spi-num-csti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplyti,non-removablebus-widthsramop-modeserial-dirti,timer-dspti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsti,iommu-bus-err-backphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertti,bootregiommusfirmware-namemboxesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infogpios#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-devicelabelpwmsmax-brightness