� ��^�8YH(=Y(,haoyu,marsboard-rk3066rockchip,rk3066a7MarsBoard RK3066aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/serial@10124000h/serial@10126000p/serial@20064000x/serial@20068000�/spi@20070000�/spi@20074000�/mmc@10214000oscillator ,fixed-clock�n6��xin24m�Egpu@10090000",rockchip,rk3066-maliarm,mali-400� ��� �buscore�����x  disabledx5gpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3,video-codec@10104000,rockchip,rk3066-vpu�@   vepuvdpu �����(�aclk_vdpuhclk_vdpuaclk_vepuhclk_vepu,cache-controller@10138000,arm,pl310-cache��:H�8scu@1013c000,arm,cortex-a9-scu��global-timer@1013c200,arm,cortex-a9-global-timer��   �local-timer@1013c600,arm,cortex-a9-twd-timer��   �interrupt-controller@1013d000,arm,cortex-a9-gicTi����serial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart�@ "z��baudclkapb_pclk�@L okay��txrx�default�serial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart�` #z��baudclkapb_pclk�AM okay��txrx�default�qos@1012d000,rockchip,rk3066-qossyscon�� �!qos@1012e000,rockchip,rk3066-qossyscon�� � qos@1012f000,rockchip,rk3066-qossyscon�� �qos@1012f080,rockchip,rk3066-qossyscon��� �qos@1012f100,rockchip,rk3066-qossyscon�� �qos@1012f180,rockchip,rk3066-qossyscon�� �qos@1012f200,rockchip,rk3066-qossyscon�� �qos@1012f280,rockchip,rk3066-qossyscon�� �usb@10180000,rockchip,rk3066-usbsnps,dwc2� ���otg�otg�����@@ � �usb2-phy okayusb@101c0000 ,snps,dwc2� ���otg�host� �usb2-phy okayethernet@10204000,rockchip,rk3066-emac� @< � ��D �hclkmacref drmii okay # �default � ethernet-phy@0�� mmc@10214000,rockchip,rk2928-dw-mshc�!@ ��H�biuciu��rx-tx.Q9reset okay����E����default�Smmc@10218000,rockchip,rk2928-dw-mshc�!� ��I�biuciu��rx-tx.R9reset  disabled�default�mmc@1021c000,rockchip,rk2928-dw-mshc�!� ��J�biuciu��rx-tx.S9reset  disablednand-controller@10500000,rockchip,rk2928-nfc�P@ ���ahb  disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd� @reboot-mode,syscon-reboot-mode_@fRB�rRB��RB� �RB�power-controller!,rockchip,rk3066-power-controller��power-domain@7���������P��O���������power-domain@6� ������ �power-domain@8����!�grf@20008000&,rockchip,rk3066-grfsysconsimple-mfd� �� usbphy,rockchip,rk3066a-usb-phy okayusb-phy@17c�|�Q�phyclk���usb-phy@188���R�phyclk���dma-controller@20018000,arm,pl330arm,primecell� �@����� �apb_pclk�dma-controller@2001c000,arm,pl330arm,primecell� �@����� �apb_pclk  disabledi2c@2002d000,rockchip,rk3066-i2c� � (� �i2c�P  disabled�default�"i2c@2002f000,rockchip,rk3066-i2c� � )� �Q�i2c okay�default�#��tps@2d�-$�% %%#%/&;&G%S% ,ti,tps65910regulatorsregulator@0`vcc_rtco��vrtcregulator@1`vcc_ioo��vio�&regulator@2`vdd_arm� '���`�o��vdd1�9regulator@3`vcc_ddr� '���`�o��vdd2regulator@5 `vcc18_cifo��vdig1regulator@6`vdd_11o��vdig2regulator@7`vcc_25o��vpllregulator@8`vcc_18o��vdacregulator@9 `vcc25_hdmio� �vaux1regulator@10`vcca_33o� �vaux2regulator@11 `vcc_rmii� �vaux33� regulator@12 `vcc28_cifo� �vmmcregulator@4��vdd3regulator@13� �vbbpwm@20030000,rockchip,rk2928-pwm� ��F  disabled�default�'pwm@20030010,rockchip,rk2928-pwm� ��F  disabled�default�(watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt� ��K 3 okaypwm@20050020,rockchip,rk2928-pwm�  ��G  disabled�default�)pwm@20050030,rockchip,rk2928-pwm� 0��G okay�default�*�Hi2c@20056000,rockchip,rk3066-i2c� ` *� �R�i2c  disabled�default�+i2c@2005a000,rockchip,rk3066-i2c� � +� �S�i2c  disabled�default�,i2c@2005e000,rockchip,rk3066-i2c� � 4� �T�i2c  disabled�default�-serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart� @ $z��baudclkapb_pclk�BN okay��txrx�default�.serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart� � %z��baudclkapb_pclk�CO okay� �txrx�default�/saradc@2006c000,rockchip,saradc� � ��GJ�saradcapb_pclkW 9saradc-apb  disabledspi@20070000,rockchip,rk3066-spi�EH�spiclkapb_pclk &� �  �txrx  disabled�default�0123spi@20074000,rockchip,rk3066-spi�FI�spiclkapb_pclk '� @�  �txrx  disabled�default�4567dma-controller@20078000,arm,pl330arm,primecell� �@����� �apb_pclk�cpus�rockchip,rk3066-smpcpu@0cpu,arm,cortex-a98�8"�@� O���a�*� s�*� '���������g83�@�A9cpu@1cpu,arm,cortex-a98�A9display-subsystem,rockchip,display-subsystemL:;sram@10080000 ,mmio-sram� Rsmp-sram@0,rockchip,rk3066-smp-sram�Pvop@1010c000,rockchip,rk3066-vop���  �����aclk_vopdclk_vophclk_vop,def 9axiahbdclk  disabledport�:endpoint@0�Y<�@vop@1010e000,rockchip,rk3066-vop��� �����aclk_vopdclk_vophclk_vop,ghi 9axiahbdclk  disabledport�;endpoint@0�Y=�Ahdmi@10116000,rockchip,rk3066-hdmi�`  @���hclk�default�>?,�   disabledportsport@0�endpoint@0�Y@�<endpoint@1�YA�=port@1�i2s@10118000,rockchip,rk3066-i2s��  �default�B�K��i2s_clki2s_hclk��txrxi��  disabledi2s@1011a000,rockchip,rk3066-i2s��   �default�C�L��i2s_clki2s_hclk��txrxi��  disabledi2s@1011c000,rockchip,rk3066-i2s��  �default�D�M��i2s_clki2s_hclk�  �txrxi��  disabledclock-controller@20000000,rockchip,rk3066a-cru� �E�xin24m� ��@���^��_ �ׄ#g����рxh���рxh��timer@2000e000,snps,dw-apb-timer� � .�VD �timerpclkefuse@20010000,rockchip,rk3066a-efuse� @�[ �pclk_efusecpu_leakage@17�timer@20038000,snps,dw-apb-timer� � ,�TB �timerpclktimer@2003a000,snps,dw-apb-timer� � -�UC �timerpclktsadc@20060000,rockchip,rk3066-tsadc� �]]�saradcapb_pclk �\ 9saradc-apb  disabledpinctrl,rockchip,rk3066a-pinctrl� Rgpio@20034000,rockchip,gpio-bank� @ 6�U��Tigpio@2003c000,rockchip,gpio-bank� � 7�V��Ti�gpio@2003e000,rockchip,gpio-bank� � 8�W��Tigpio@20080000,rockchip,gpio-bank�  9�X��Ti�Igpio@20084000,rockchip,gpio-bank� @ :�Y��Tigpio@2000a000,rockchip,gpio-bank� � <�Z��Ti�$pcfg-pull-default��Gpcfg-pull-none��Femacemac-xfer��FFFFFFFF� emac-mdio �FF� emmcemmc-clk�Gemmc-cmd� Gemmc-rst� Ghdmihdmi-hpd�G�?hdmii2c-xfer �FF�>i2c0i2c0-xfer �FF�"i2c1i2c1-xfer �FF�#i2c2i2c2-xfer �FF�+i2c3i2c3-xfer �FF�,i2c4i2c4-xfer �FF�-pwm0pwm0-out�F�'pwm1pwm1-out�F�(pwm2pwm2-out�F�)pwm3pwm3-out�F�*spi0spi0-clk�G�0spi0-cs0�G�3spi0-tx�G�1spi0-rx�G�2spi0-cs1�Gspi1spi1-clk�G�4spi1-cs0�G�7spi1-rx�G�6spi1-tx�G�5spi1-cs1�Guart0uart0-xfer �GG�uart0-cts�Guart0-rts�Guart1uart1-xfer �GG�uart1-cts�Guart1-rts�Guart2uart2-xfer �G G�.uart3uart3-xfer �GG�/uart3-cts�Guart3-rts�Gsd0sd0-clk�G�sd0-cmd� G�sd0-cd�G�sd0-wp�Gsd0-bus-width1� Gsd0-bus-width4@� G G G G�sd1sd1-clk�G�sd1-cmd�G�sd1-cd�G�sd1-wp�Gsd1-bus-width1�Gsd1-bus-width4@�GGGG�i2s0i2s0-bus��GG G G G G GGG�Bi2s1i2s1-bus`�GGGGGG�Ci2s2i2s2-bus`�GGGGGG�Dlan8720aphy-int�F�memory@60000000memory�`@vdd-log,pwm-regulator  H�`vdd_log�O��O�oB@dO�* okaysdmmc-regulator,regulator-fixed `sdmmc-supply�-���-�� I!��2&�vsys-regulator,regulator-fixed`vsys�LK@�LK@��% #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1mmc0clock-frequency#clock-cellsclock-output-namesphandleregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthreset-namesmax-frequencyvmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsrangesremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supply