� ��O�8L (�K�7xlnx,zynqmp-zc1275-revAxlnx,zynqmp-zc1275xlnx,zynqmp &ZynqMP ZC1275 RevAcpus cpu@0arm,cortex-a53,cpu8psciFZ^n cpu@1arm,cortex-a53,cpu8psciZF^cpu@2arm,cortex-a53,cpu8psciZF^cpu@3arm,cortex-a53,cpu8psciZF^idle-statesupscicpu-sleep-0arm,idle-state�@��,�X�'�cpu-opp-tableoperating-points-v2��opp00�G����B@� opp01�#�E��B@� opp02�׃��B@� opp03����B@� zynqmp_ipixlnx,zynqmp-ipi-mailbox &#1 =mailbox@ff990400@Z��� ��� ��� ��� XDlocal_request_regionlocal_response_regionremote_request_regionremote_response_regionN1�dccarm,dccZokaypmuarm,armv8-pmuv30&����psci arm,psci-0.2?smcfirmwarezynqmp-firmwarexlnx,zynqmp-firmwarea?smc� zynqmp-powerxlnx,zynqmp-power &#u|txrxnvmem_firmwarexlnx,zynqmp-nvmem-fw soc_revision@0Zpcapxlnx,zynqmp-pcap-fpga� zynqmp-aesxlnx,zynqmp-aesreset-controllerxlnx,zynqmp-reset��pinctrlxlnx,zynqmp-pinctrl Zdisabledclock-controller�xlnx,zynqmp-clkn A�pss_ref_clkvideo_clkpss_alt_ref_clkaux_ref_clkgt_crx_ref_clk�timerarm,armv8-timer0&   fpga-full fpga-region�  =axi simple-bus =can@ff060000xlnx,zynq-can-1.0 Zdisabled �can_clkpclkZ� &�@�@� /n?can@ff070000xlnx,zynq-can-1.0 Zdisabled �can_clkpclkZ� &�@�@� 0n@cci@fd6e0000 arm,cci-400 ZdisabledZ�n�=�n pmu@9000arm,cci-400-pmu,r1Z�P<&{{{{{dma-controller@fd500000 Zdisabledxlnx,zynqmp-dma-1.0Z�P &|�clk_mainclk_apb���� �� *ndma-controller@fd510000 Zdisabledxlnx,zynqmp-dma-1.0Z�Q &}�clk_mainclk_apb���� �� *ndma-controller@fd520000 Zdisabledxlnx,zynqmp-dma-1.0Z�R &~�clk_mainclk_apb���� �� *ndma-controller@fd530000 Zdisabledxlnx,zynqmp-dma-1.0Z�S &�clk_mainclk_apb���� �� *ndma-controller@fd540000 Zdisabledxlnx,zynqmp-dma-1.0Z�T &��clk_mainclk_apb���� �� *ndma-controller@fd550000 Zdisabledxlnx,zynqmp-dma-1.0Z�U &��clk_mainclk_apb���� �� *ndma-controller@fd560000 Zdisabledxlnx,zynqmp-dma-1.0Z�V &��clk_mainclk_apb���� �� *ndma-controller@fd570000 Zdisabledxlnx,zynqmp-dma-1.0Z�W &��clk_mainclk_apb���� �� *ninterrupt-controller@f9010000 arm,gic-400 @Z���� & �dma-controller@ffa80000 Zdisabledxlnx,zynqmp-dma-1.0Z�� &M�clk_mainclk_apb��@� h� +nDdma-controller@ffa90000 Zdisabledxlnx,zynqmp-dma-1.0Z�� &N�clk_mainclk_apb��@� i� +nDdma-controller@ffaa0000 Zdisabledxlnx,zynqmp-dma-1.0Z�� &O�clk_mainclk_apb��@� j� +nDdma-controller@ffab0000 Zdisabledxlnx,zynqmp-dma-1.0Z�� &P�clk_mainclk_apb��@� k� +nDdma-controller@ffac0000 Zdisabledxlnx,zynqmp-dma-1.0Z�� &Q�clk_mainclk_apb��@� l� +nDdma-controller@ffad0000 Zdisabledxlnx,zynqmp-dma-1.0Z�� &R�clk_mainclk_apb��@� m� +nDdma-controller@ffae0000 Zdisabledxlnx,zynqmp-dma-1.0Z�� &S�clk_mainclk_apb��@� n� +nDdma-controller@ffaf0000 Zdisabledxlnx,zynqmp-dma-1.0Z�� &T�clk_mainclk_apb��@� o� +nDmemory-controller@fd070000xlnx,zynqmp-ddrc-2.40aZ� &pnand-controller@ff100000-xlnx,zynqmp-nand-controllerarasan,nfc-v3p10 ZdisabledZ��controllerbus & � r� ,n<ethernet@ff0b0000cdns,zynqmp-gemcdns,gem Zdisabled&99Z�  �pclkhclktx_clkrx_clktsu_clk � t� ' .gem0_rst(nh-1,ethernet@ff0c0000cdns,zynqmp-gemcdns,gem Zdisabled&;;Z�  �pclkhclktx_clkrx_clktsu_clk � u� ' .gem1_rst(ni.2,ethernet@ff0d0000cdns,zynqmp-gemcdns,gem Zdisabled&==Z�  �pclkhclktx_clkrx_clktsu_clk � v� ' .gem2_rst(nj/3,ethernet@ff0e0000cdns,zynqmp-gemcdns,gem Zdisabled&??Z� �pclkhclktx_clkrx_clktsu_clk � w� '  .gem3_rst(nk04,gpio@ff0a0000xlnx,zynqmp-gpio-1.0Zokay :F &Z� � .ni2c@ff020000cdns,i2c-r1p14 Zdisabled &Z� � %n=i2c@ff030000cdns,i2c-r1p14 Zdisabled &Z� � &n>pcie@fd0e0000xlnx,nwl-pcie-2.11 Zdisabled V,pci<&vutsremiscdummyintxmsi1msi0u0Z��H�Dbregpciregcfg8=��C���`�� �� ;n�legacy-interrupt-controller �spi@ff0f0000xlnx,zynqmp-qspi-1.0Zokay �ref_clkpclk &� Z�� � s� -n5flash@0m25p80jedec,spi-norZ���o�phy@fd400000xlnx,zynqmp-psgtr-v1.1 Zdisabled Z�@�= Dserdessiou�rtc@ffa60000xlnx,zynqmp-rtc ZdisabledZ��& ealarmsec��ahci@fd0c0000ceva,ahci-1v84 ZdisabledZ�  &�� ' � � � � �nmmc@ff160000#xlnx,zynqmp-8.9aarasan,sdhci-8.9a Zdisabled &0Z��clk_xinclk_ahb� p��clk_out_sd0clk_in_sd0� 'n6mmc@ff170000#xlnx,zynqmp-8.9aarasan,sdhci-8.9a Zdisabled &1Z��clk_xinclk_ahb� q��clk_out_sd1clk_in_sd1� (n7iommu@fd800000 arm,mmu-500Z�� Zdisabled�&������������������ spi@ff040000cdns,spi-r1p6 Zdisabled &Z� �ref_clkpclk � #n:spi@ff050000cdns,spi-r1p6 Zdisabled &Z� �ref_clkpclk � $n;timer@ff110000 cdns,ttc Zdisabled$&$%&Z�0 � ntimer@ff120000 cdns,ttc Zdisabled$&'()Z�0 � ntimer@ff130000 cdns,ttc Zdisabled$&*+,Z�0 � ntimer@ff140000 cdns,ttc Zdisabled$&-./Z�0 � nserial@ff000000!xlnx,zynqmp-uartcdns,uart-r1p12Zokay &Z��uart_clkpclk� !n8serial@ff010000!xlnx,zynqmp-uartcdns,uart-r1p12 Zdisabled &Z��uart_clkpclk� "n9usb@ff9d0000  Zdisabledxlnx,zynqmp-dwc3Z��� ';=?.usb_crstusb_hibrstusb_apbrst=usb@fe200000 snps,dwc3Z�  edwc_usb3otg&AE�bus_earlyref� `< _n "usb@ff9e0000  Zdisabledxlnx,zynqmp-dwc3Z��� '<>@.usb_crstusb_hibrstusb_apbrst=usb@fe300000 snps,dwc3Z�0 edwc_usb3otg&FJ�bus_earlyref� a< _n!"watchdog@fd4d0000cdns,wdt-r1p2 Zdisabled &qZ�M{<�nKwatchdog@ff150000cdns,wdt-r1p2 Zdisabled &4Z�{ npams@ffa50000xlnx,zynqmp-ams Zdisabled &8Z�� �=��nFams_ps@0xlnx,zynqmp-ams-ps ZdisabledZams_pl@400xlnx,zynqmp-ams-pl ZdisabledZ dma-controller@fd4c0000xlnx,zynqmp-dpdma ZdisabledZ�L &z�axi_clk� )�n�display@fd4a0000xlnx,zynqmp-dpsub-1.7 Zdisabled@Z�J�J��J��J�Ddpblendav_bufaud &w*�dp_apb_clkdp_aud_clkdp_vtc_pixel_clk_in� )'�vid0vid1vid2gfx0 �npss_ref_clk fixed-clock����U�video_clk fixed-clock������pss_alt_ref_clk fixed-clock���gt_crx_ref_clk fixed-clock��o�� aux_ref_clk fixed-clock������ aliases�/axi/serial@ff000000�/dcc�/axi/spi@ff0f0000chosen �earlycon�serial0:115200n8memory@0,memoryZ� compatible#address-cells#size-cellsmodeldevice_typeenable-methodoperating-points-v2regcpu-idle-statesclocksentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usphandleopp-sharedopp-hzopp-microvoltclock-latency-nsinterrupt-parentinterruptsxlnx,ipi-idrangesreg-names#mbox-cellsstatus#power-domain-cellsmboxesmbox-names#reset-cells#clock-cellsclock-namesfpga-mgrtx-fifo-depthrx-fifo-depthpower-domains#dma-cellsxlnx,bus-widthiommus#interrupt-cellsinterrupt-controllerresetsreset-names#gpio-cellsgpio-controllermsi-controllerinterrupt-namesmsi-parentbus-rangeinterrupt-map-maskinterrupt-mapnum-csspi-tx-bus-widthspi-rx-bus-widthspi-max-frequency#phy-cellscalibrationclock-output-names#iommu-cells#global-interruptstimer-widthsnps,quirk-frame-length-adjustmentsnps,resume-hs-terminationstimeout-secreset-on-timeout#io-channel-cellsdma-namesdmasclock-frequencyserial0serial1spi0bootargsstdout-path