� ��ݗ8�( �� ,anbernic,rg503rockchip,rk35667RG503aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000�/serial@fe660000�/serial@fe670000�/serial@fe680000�/serial@fe690000�/serial@fe6a0000�/serial@fe6b0000�/serial@fe6c0000�/serial@fe6d0000�/spi@fe610000�/spi@fe620000�/spi@fe630000�/spi@fe640000�/mmc@fe2b0000�/mmc@fe2c0000�/mmc@fe000000cpus cpu@0�cpu,arm,cortex-a55��psci 4? cpu@100�cpu,arm,cortex-a55�psci 4? cpu@200�cpu,arm,cortex-a55�psci 4? cpu@300�cpu,arm,cortex-a55�psci 4? opp-table-0,operating-points-v2G?opp-408000000RQ� Y �� ���0g�@opp-600000000R#�F Y �� ���0opp-816000000R0�, Y �� ���0xopp-1104000000RAʹ Y �� ���0opp-1416000000RTfr Y �� ���0opp-1608000000R_�" Y�����0opp-1800000000RkI� Y���0display-subsystem,rockchip,display-subsystem�firmwarescmi ,arm,scmi-smc��� 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�������usb �disabledusb@fd840000 ,generic-ohci��� �������usb �disabledusb@fd880000 ,generic-ehci��� �������usb�okayusb@fd8c0000 ,generic-ohci��� �������usb�okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd���?�io-domains&,rockchip,rk3568-pmu-io-voltage-domain�okayESao}���syscon@fdc50000��� ,rockchip,rk3566-pipe-grfsyscon?�syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd���?syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsyscon���?�syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsyscon���?�syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsyscon����?�syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsyscon��ʀ�?�clock-controller@fdd00000,rockchip,rk3568-pmucru�����?clock-controller@fdd20000,rockchip,rk3568-cru����zxin24m����G�� ���?i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c��� .�- zi2cpclk[edefault �okaypmic@20,rockchip,rk817�  Hrk808-clkout1rk808-clkout2zmclk�H�H��� edefault[!"*#6#B#N#Z#f#r#~#�$?�regulatorsDCDC_REG1���� ��p� ��q 1vdd_logicregulator-state-mem@Y ��DCDC_REG2���� ��p� ��q1vdd_gpu?Cregulator-state-mem@DCDC_REG3��1vcc_ddrregulator-state-memuDCDC_REG4���2Z��2Z�1vcc_3v3?regulator-state-memuY2Z�LDO_REG1���w@�w@ 1vcca1v8_pmu?Kregulator-state-memuYw@LDO_REG2��� ��� �� 1vdda_0v9regulator-state-mem@LDO_REG3��� ��� �� 1vdda0v9_pmuregulator-state-memuY ��LDO_REG4���2Z��2Z� 1vccio_acodec?regulator-state-mem@LDO_REG5���w@�2Z� 1vccio_sd?regulator-state-mem@LDO_REG6���2Z��2Z� 1vcc3v3_pmu?regulator-state-memuY2Z�LDO_REG7���w@�w@1vcc_1v8?regulator-state-mem@LDO_REG8���w@�2Z� 1vcc1v8_dvp?regulator-state-mem@LDO_REG9���*���*�� 1vcc2v8_dvpregulator-state-mem@BOOST���G�`�Re�1boost?$regulator-state-mem@OTG_SWITCH 1otg_switchregulator-state-mem@regulator@40 ,fcs,fan53555�@���� �4�5�� ��1vdd_cpu��#?regulator-state-mem@serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart��� t� ,zbaudclkapb_pclk�%%[&edefault�� �disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm���� 0 zpwmpclk['edefault� �disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm���� 0 zpwmpclk[(edefault� �disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��� � 0 zpwmpclk[)edefault� �disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm���0� 0 zpwmpclk[*edefault� �disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfd���power-controller!,rockchip,rk3568-power-controller� ?power-domain@7���+�power-domain@8���� �,-.�power-domain@9� ���� �/01�power-domain@10� ����234567�power-domain@11� ���8�power-domain@13�� �9�power-domain@14�� �:;<�power-domain@15���=>?@A�gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost���@$()' �jobmmugpu�zgpubus B��okayC?�video-codec@fdea0400,rockchip,rk3568-vpu��� ���� zaclkhclkD� iommu@fdea0800,rockchip,rk3568-iommu���@ � zaclkiface���� ?Dvideo-codec@fdee0000,rockchip,rk3568-vepu��� @��� zaclkhclkE� iommu@fdee0800,rockchip,rk3568-iommu���@ ?��� zaclkiface� ?Emmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc��@ d �����zbiuciuciu-driveciu-sample'2�р��@reset�okayLVgt�F� [GHIedefault�J�Kethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a�� �macirqeth_wake_irq@���������Wzstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref�� @stmmaceth��L��M�N �disabledmdio,snps,dwmac-mdio stmmac-axi-config &?Lrx-queues-config6?Mqueue0tx-queues-configL?Nqueue0vop@fe040000 ��0�@bvopgamma-lut �(������%zaclkhclkdclk_vp0dclk_vp1dclk_vp2O� ��okay,rockchip,rk3566-vop����ports ?port@0� endpoint@2�lP?Uport@1� port@2� iommu@fe043e00,rockchip,rk3568-iommu ��>�? ���� zaclkiface�okay?Odsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi�� D zpclkhclk����dphy�Q� @apb�� �disabledports port@0�port@1�dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi�� E zpclkhclk����dphy�R� @apb�� �disabledports port@0�port@1�hdmi@fe0a0000,rockchip,rk3568-dw-hdmi��  -(����(�ziahbisfrcecrefedefault[S� �� �okay|T?ports port@0�endpointlU?Pport@1�endpointlV?�qos@fe128000,rockchip,rk3568-qossyscon��� ?+qos@fe138080,rockchip,rk3568-qossyscon���� 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?1pcie@fe260000,rockchip,rk3568-pcie0��@�&?bdbiapbconfig<KJIHG�syspmcmsilegacyerr�(������$zaclk_mstaclk_slvaclk_dbipclkaux�pci�`�WWWW������� �pcie-phy�8s>�>�>���@pipe  �disabledlegacy-interrupt-controller� H?Wmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc��+@ b �����zbiuciuciu-driveciu-sample'2�р��@reset�okayLV   [XYZ[edefault��mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc��,@ c �����zbiuciuciu-driveciu-sample'2�р��@reset�okayLV \  []^_`edefault��spi@fe300000 ,rockchip,sfc��0@ e�xvzclk_sfchclk_sfc[aedefault �disabledmmc@fe310000,rockchip,rk3568-dwcmshc��1 �{}� ��n6(�|zy{}zcorebusaxiblocktimer �disabledi2s@fe400000,rockchip,rk3568-i2s-tdm��@ 4�=A�F�qF�q�?C9zmclk_txmclk_rxhclk�b%tx�PQ @tx-mrx-m� �okay?i2s@fe410000,rockchip,rk3568-i2s-tdm��A 5�EI�F�qF�q�GK:zmclk_txmclk_rxhclk�bb%rxtx�RS @tx-mrx-m�edefault[cdef �okay/?�i2s@fe420000,rockchip,rk3568-i2s-tdm��B 6�M�F�q�OO;zmclk_txmclk_rxhclk�bb%txrx�T@m�edefault[ghij  �disabledi2s@fe430000,rockchip,rk3568-i2s-tdm��C 7�SW<zmclk_txmclk_rxhclk�bb%txrx�UV @tx-mrx-m�  �disabledpdm@fe440000,rockchip,rk3568-pdm��D L�ZYzpdm_clkpdm_hclk�b %rx[klmnopedefault�X@pdm-m  �disabledspdif@fe460000,rockchip,rk3568-spdif��F f zmclkhclk�_\�b%txedefault[q  �disableddma-controller@fe530000,arm,pl330arm,primecell��S@ J�  zapb_pclka?%dma-controller@fe550000,arm,pl330arm,primecell��U@J�  zapb_pclka?bi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��Z /�HG zi2cpclk[redefault  �disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��[ 0�JI zi2cpclk[sedefault  �disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��\ 1�LK zi2cpclk[tedefault  �disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��] 2�NM zi2cpclk[uedefault  �disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��^ 3�PO zi2cpclk[vedefault �okay?Twatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt��` �� ztclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spi��a g�RQzspiclkapb_pclk�%%%txrxedefault [wxy  �disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spi��b h�TSzspiclkapb_pclk�%%%txrxedefault [z{|  �disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spi��c i�VUzspiclkapb_pclk�%%%txrxedefault [}~  �disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spi��d j�XWzspiclkapb_pclk�%%%txrxedefault [���  �disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uart��e u�zbaudclkapb_pclk�%% [���edefault���okaylbluetooth,realtek,rtl8821cs-bt |� �� ��serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uart��f v�# zbaudclkapb_pclk�%%[�edefault���okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uart��g w�'$zbaudclkapb_pclk�%%[�edefault�� �disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uart��h x�+(zbaudclkapb_pclk�%% [�edefault�� �disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uart��i y�/,zbaudclkapb_pclk�% % [�edefault�� �disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uart��j z�30zbaudclkapb_pclk�% % [�edefault�� �disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uart��k {�74zbaudclkapb_pclk�%%[�edefault�� �disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uart��l |�;8zbaudclkapb_pclk�%%[�edefault�� �disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uart��m }�?<zbaudclkapb_pclk�%%[�edefault�� �disabledthermal-zonescpu-thermal�d����tripscpu_alert0�p���passive?�cpu_alert1�$����passivecpu_crit�s�� �criticalcooling-mapsmap0��0� �������� �������� �������� ��������gpu-thermal�����tripsgpu-threshold�p���passivegpu-target�$����passive?�gpu-crit�s�� �criticalcooling-mapsmap0�� ����������tsadc@fe710000,rockchip,rk3568-tsadc��q s��f@ �`�ztsadcapb_pclk����� seinitdefaultsleep[� !� +� 5�okay K b?�saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradc��r ]�zsaradcapb_pclk�� @saradc-apb }�okay �?�pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��n�ZY zpwmpclk[�edefault� �disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��n�ZY zpwmpclk[�edefault��okay?�pwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��n �ZY zpwmpclk[�edefault� �disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm��n0�ZY zpwmpclk[�edefault� �disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o�]\ zpwmpclk[�edefault� �disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o�]\ zpwmpclk[�edefault� �disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o �]\ zpwmpclk[�edefault� �disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o0�]\ zpwmpclk[�edefault� �disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p�`_ zpwmpclk[�edefault� �disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p�`_ zpwmpclk[�edefault� �disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p �`_ zpwmpclk[�edefault� �disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p0�`_ zpwmpclk[�edefault� �disabledphy@fe830000,rockchip,rk3568-naneng-combphy����"} zrefapbpipe�"����� �� �� ��okay?phy@fe840000,rockchip,rk3568-naneng-combphy����%~ zrefapbpipe�%����� �� �� � �disabled?phy@fe870000,rockchip,rk3568-csi-dphy����yzpclk ���@apb� �disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy��� zrefpclk�z �� @apb�� �disabled?Qmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy��� zrefpclk�{ �� @apb�� �disabled?Rusb2phy@fe8a0000,rockchip,rk3568-usb2phy����zphyclkHclk_usbphy0_480m � ����okay?host-port � �disabledotg-port ��okay?usb2phy@fe8b0000,rockchip,rk3568-usb2phy����zphyclkHclk_usbphy1_480m � ����okayhost-port ��okay?otg-port � �disabled?pinctrl,rockchip,rk3568-pinctrl� �� sgpio@fdd60000,rockchip,gpio-bank��� !�.  � ��? gpio@fe740000,rockchip,gpio-bank��t "�cd � ��gpio@fe750000,rockchip,gpio-bank��u #�ef � ��?\gpio@fe760000,rockchip,gpio-bank��v $�gh � ��?�gpio@fe770000,rockchip,gpio-bank��w %�ij � ��?�pcfg-pull-up ?�pcfg-pull-none ?�pcfg-pull-none-drv-level-1  !?�pcfg-pull-none-drv-level-2  !?�pcfg-pull-none-drv-level-3  !?�pcfg-pull-up-drv-level-1  !?�pcfg-pull-up-drv-level-2 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