� ���Q8�( u� zkmagic,a95x-z2rockchip,rk3318 +7A95X Z2aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000�/mmc@ff510000�/mmc@ff520000cpus+cpu@0�cpuarm,cortex-a53�����x�psci�� cpu@1�cpuarm,cortex-a53�����x�psci�� cpu@2�cpuarm,cortex-a53�����x�psci�� cpu@3�cpuarm,cortex-a53�����x�psci�� idle-states"pscicpu-sleeparm,idle-state/@Wxh�x�l2-cache0cacheopp-table-0operating-points-v2�opp-408000000�Q��~���@�opp-600000000�#�F�~���@opp-816000000�0�,�B@��@opp-1008000000�<������@opp-1200000000�G����(��@ �disabledopp-1296000000�M?d�� ��@ �disabledanalog-soundsimple-audio-card�i2s�Analog�okaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0!defg, display-subsystemrockchip,display-subsystem? hdmi-soundsimple-audio-card�i2s��HDMI�okaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2�smctimerarm,armv8-timer0!   xin24m fixed-clockERn6bxin24m@i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s�� !�)7ui2s_clki2s_hclk�  �txrx��okayi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s�� !�*8ui2s_clki2s_hclk��txrx��okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s�� !�+9ui2s_clki2s_hclk��txrx� �disabledspdif@ff030000rockchip,rk3328-spdif�� !�.: umclkhclk� �tx�default���okaygpdm@ff040000 rockchip,pdm���=Rupdm_clkpdm_hclk��rx�defaultsleep�� �disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd��4io-domains"rockchip,rk3328-io-voltage-domain�okay�����gpiorockchip,rk3328-grf-gpio$4power-controller!rockchip,rk3328-power-controller@+7power-domain@6�@power-domain@5� ��BAB@power-domain@8���F@reboot-modesyscon-reboot-modeT�[RB�gRB�uRB� �RB�serial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart�� !7�&�ubaudclkapb_pclk��txrx�default����okayserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart�� !8�'�ubaudclkapb_pclk��txrx�default � !"�� �disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart�� !9�(�ubaudclkapb_pclk��txrx�default�#���okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c�� !$+�7� ui2cpclk�default�$ �disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c�� !%+�8� ui2cpclk�default�% �disabledi2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c�� !&+�9� ui2cpclk�default�& �disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c�� !'+�:� ui2cpclk�default�' �disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi�� !1+� �uspiclkapb_pclk� �txrx�default�()*+ �disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt�� !(��pwm@ff1b0000rockchip,rk3328-pwm���<� upwmpclk�active�,��okaylpwm@ff1b0010rockchip,rk3328-pwm���<� upwmpclk�active�-��okaympwm@ff1b0020rockchip,rk3328-pwm�� �<� upwmpclk�default�.� �disabledpwm@ff1b0030rockchip,rk3328-pwm��0 !2�<� upwmpclk�default�/� �disableddma-controller@ff1f0000arm,pl330arm,primecell��@!��� uapb_pclk�thermal-zonessoc-thermal����� 0tripstrip-point0_�'��passivetrip-point1�('��passive1soc-crit�8'� �criticalcooling-mapsmap02107 �������� �������� �������� ��������Ftsadc@ff250000rockchip,rk3328-tsadc��% !:S$c�P�$�utsadcapb_pclk�initdefaultsleep�2�3x2�B �tsadc-apb�4�����okay0efuse@ff260000rockchip,rk3328-efuse��&P+�> upclk_efuse� id@7�cpu-leakage@17�logic-leakage@19�cpu-version@1a��Aadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc��( !P��%�usaradcapb_pclk�V �saradc-apb�okay�agpu@ff300000"rockchip,rk3328-maliarm,mali-450��0T!ZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1��� ubuscore�f5iommu@ff330200rockchip,iommu��3 !`��� uaclkiface" �disablediommu@ff340800rockchip,iommu��4@ !b��F uaclkiface" �disabledvideo-codec@ff350000rockchip,rk3328-vpu��5 ! vdpu��F uaclkhclk/667iommu@ff350800rockchip,iommu��5@ ! ��F uaclkiface"676video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec��6 ! ��BABuaxiahbcabaccoreS�AB cׄׄ�/867iommu@ff360480rockchip,iommu ��6�@�6�@ !J��B uaclkiface"678vop@ff370000rockchip,rk3328-vop��7>� ! ��x;uaclk_vopdclk_vophclk_vop���� �axiahbdclk/9�okayport+ endpoint@0�D:?iommu@ff373f00rockchip,iommu��7? ! ��; uaclkiface"�okay9hdmi@ff3c0000rockchip,rk3328-dw-hdmi��<�!#G��FuiahbisfrcecT;Yhdmi�default �<=>�4��okayportsportendpointD?:codec@ff410000rockchip,rk3328-codec��A��* upclkmclk�4��okayphy@ff430000rockchip,rk3328-hdmi-phy��C !S��@yusysclkrefoclkrefpclk bhdmi_phyEcA ocpu-version��okay;clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon��D�4E��Sx=&'(��������ABDC"\5�H��4�$�z@@@|c��n6n6n6�����������������������������������n6#�FLG���рxh�xh��рxh�xh��syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd��E+usb2phy@100rockchip,rk3328-usb2phy��@uphyclk busb480m_phyES{�B�okayBotg-port�$!;<=otg-bvalidotg-idlinestate�okay�CThost-port� !> linestate�okayUmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc��P@ !  �=!JNubiuciuciu-driveciu-sample���р�okay���DEFG�default�Hmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc��Q@ !  �>"KOubiuciuciu-driveciu-sample��sY@�okay���I(�JKLM�default6mmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc��R@ ! �?#LPubiuciuciu-driveciu-sample���р�okay�D( �NOP�defaultethernet@ff540000rockchip,rk3328-gmac��T !macirq8�dWXZY��Mustmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac�c �stmmaceth�4V �disabledethernet@ff550000rockchip,rk3328-gmac��U�4 !macirq8�TSSU��VIustmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy�b �stmmacetharmiijQVuoutput�okay�T����Semdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22��V�d�default�RS�Qusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2��X !�Muotg�host�����@ TT Yusb2-phy�okayusb@ff5c0000 generic-ehci��\ ! �NBTUYusb�okayusb@ff5d0000 generic-ohci��] ! �NBTUYusb�okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3��` !C�`a�uref_clksuspend_clkbus_clk�host �utmi_wide� "De~�okayinterrupt-controller@ff811000 arm,gic-400��@����� ��@ ��`  ! pinctrlrockchip,rk3328-pinctrl�4+�gpio@ff210000rockchip,gpio-bank��! !3��$4��igpio@ff220000rockchip,gpio-bank��" !4��$4��fgpio@ff230000rockchip,gpio-bank��# !5��$4��bgpio@ff240000rockchip,gpio-bank��$ !6��$4��pcfg-pull-up�Xpcfg-pull-down�`pcfg-pull-none�Vpcfg-pull-none-2ma��_pcfg-pull-up-2ma��pcfg-pull-up-4ma��Ypcfg-pull-none-4ma��\pcfg-pull-down-4ma��pcfg-pull-none-8ma��Zpcfg-pull-up-8ma��[pcfg-pull-none-12ma�� ]pcfg-pull-up-12ma�� ^pcfg-output-high�pcfg-output-lowpcfg-input-high�Wpcfg-inputi2c0i2c0-xfer  VV$i2c1i2c1-xfer  VV%i2c2i2c2-xfer   VV&i2c3i2c3-xfer  VV'i2c3-pins  VVhdmi_i2chdmii2c-xfer  VV=pdm-0pdmm0-clk Vpdmm0-fsync Vpdmm0-sdi0 Vpdmm0-sdi1 Vpdmm0-sdi2 Vpdmm0-sdi3 Vpdmm0-clk-sleep Wpdmm0-sdi0-sleep Wpdmm0-sdi1-sleep Wpdmm0-sdi2-sleep Wpdmm0-sdi3-sleep Wpdmm0-fsync-sleep Wtsadcotp-pin  V2otp-out  V3uart0uart0-xfer   VXuart0-cts  Vuart0-rts  Vuart0-rts-pin  Vuart1uart1-xfer  VX uart1-cts V!uart1-rts V"uart1-rts-pin Vuart2-0uart2m0-xfer  VXuart2-1uart2m1-xfer  VX#spi0-0spi0m0-clk Xspi0m0-cs0  Xspi0m0-tx  Xspi0m0-rx  Xspi0m0-cs1  Xspi0-1spi0m1-clk Xspi0m1-cs0 Xspi0m1-tx Xspi0m1-rx Xspi0m1-cs1 Xspi0-2spi0m2-clk X(spi0m2-cs0 X+spi0m2-tx X)spi0m2-rx X*i2s1i2s1-mclk Vi2s1-sclk Vi2s1-lrckrx Vi2s1-lrcktx Vi2s1-sdi Vi2s1-sdo Vi2s1-sdio1 Vi2s1-sdio2 Vi2s1-sdio3 Vi2s1-sleep� WWWWWWWWWi2s2-0i2s2m0-mclk Vi2s2m0-sclk Vi2s2m0-lrckrx Vi2s2m0-lrcktx Vi2s2m0-sdi Vi2s2m0-sdo Vi2s2m0-sleep` WWWWWWi2s2-1i2s2m1-mclk Vi2s2m1-sclk Vi2sm1-lrckrx Vi2s2m1-lrcktx Vi2s2m1-sdi Vi2s2m1-sdo Vi2s2m1-sleepP WWWWWspdif-0spdifm0-tx Vspdif-1spdifm1-tx Vspdif-2spdifm2-tx Vsdmmc0-0sdmmc0m0-pwren Ysdmmc0m0-pin Ysdmmc0-1sdmmc0m1-pwren Ysdmmc0m1-pin Yksdmmc0sdmmc0-clk ZDsdmmc0-cmd [Esdmmc0-dectn YFsdmmc0-wrprt Ysdmmc0-bus1 [sdmmc0-bus4@ [[[[Gsdmmc0-pins� YYYYYYYYsdmmc0extsdmmc0ext-clk \sdmmc0ext-cmd Ysdmmc0ext-wrprt Ysdmmc0ext-dectn Ysdmmc0ext-bus1 Ysdmmc0ext-bus4@ YYYYsdmmc0ext-pins� YYYYYYYYsdmmc1sdmmc1-clk  ZLsdmmc1-cmd  [Ksdmmc1-pwren [sdmmc1-wrprt [sdmmc1-dectn [sdmmc1-bus1 [sdmmc1-bus4@ [[[[Jsdmmc1-pins�  Y YYYYYYYYclk-32k-out VMemmcemmc-clk ]Nemmc-cmd ^Oemmc-pwren Vemmc-rstnout Vemmc-bus1 ^emmc-bus4@ ^^^^emmc-bus8� ^^^^^^^^Ppwm0pwm0-pin Vpwm0-pin-pull-up X,pwm1pwm1-pin Vpwm1-pin-pull-up X-pwm2pwm2-pin V.pwmirpwmir-pin V/gmac-1rgmiim1-pins`  Z \\Z\\\ \ \Z Z\\ZZZ Z\ZZZZrmiim1-pins _]____ _ _] ] V VVVVVgmac2phyfephyled-speed10 Vfephyled-duplex Vfephyled-rxm1 VRfephyled-txm1 Vfephyled-linkm1 VStsadc_pintsadc-int  Vtsadc-pin  Vhdmi_pinhdmi-cec V<hdmi-hpd `>cif-0dvp-d2d9-m0� VVVVV V V VVVVVcif-1dvp-d2d9-m1� VVVVVVVVVVVVirir-int Vcledscyx-led-pin Vdsdio-pwrseqwifi-enable-h Veusbhost-vbus-drv Votg-vbus-drv Vjchosen.serial2:1500000n8adc-keys adc-keys:aFbuttonsWw@qdbutton-recovery recovery�h�Bhir-receivergpio-ir-receiver �b�c�defaultleds gpio-leds�d�defaultled-0�on �bCYX_LEDsdio-pwrseqmmc-pwrseq-simple�e�default �fIspdif-soundsimple-audio-cardSPDIFsimple-audio-card,cpugsimple-audio-card,codechspdif-outlinux,spdif-dit�hvccio-1v8-regulatorregulator-fixed �vccio_1v8�w@�w@ vccio-3v3-regulatorregulator-fixed �vccio_3v3�2Z��2Z� otg-vbus-regulatorregulator-fixed i�j�default �vcc_otg_vbus�LK@�LK@ "Csdmmc-regulatorregulator-fixed i�k�default�vcc_sd�2Z��2Z� 5Hvdd-armpwm-regulator @l��vdd_arm�~��\� E�  cvdd-logpwm-regulator @m��vdd_log� ����  E�  c5 compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1mmc2device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstatussimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shift#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsvref-supplyinterrupt-namesmali-supply#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsphy-supplyfifo-depthmax-frequencybus-widthcap-sd-highspeedvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104cap-mmc-highspeedsnps,txpblphy-modephy-handleclock_in_outassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltgpiosdefault-statereset-gpiosregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ongpioenable-active-highvin-supplypwmsregulator-settling-time-up-usregulator-boot-on