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Z!target-module@4802e000ti,sysc-omap4-timerti,syscH�H� =revsysc�� �pGfck+ �H�cwtimer@0ti,dm816-timer�C� �pGfck�"�target-module@48040000ti,sysc-omap4-timerti,syscHH =revsysc�� �tGfck+ �Hcwtimer@0ti,dm816-timer�D �tGfck�#�timer@48042000ti,dm816-timerH �E�timer3timer@48044000ti,dm816-timerH@ �\�timer4�timer@48046000ti,dm816-timerH` �]�timer5�timer@48048000ti,dm816-timerH� �^�timer6�timer@4804a000ti,dm816-timerH� �_�timer7�uart@48020000ti,am3352-uartti,omap3-uart�uart1H e�l�H\atxrxuart@48022000ti,am3352-uartti,omap3-uart�uart2H e�l�I\atxrxuart@48024000ti,am3352-uartti,omap3-uart�uart3H@ e�l�J\atxrxusb_otg_hs@47401000ti,am33xx-usbG@@�+ �usb_otg_hsusb@47401000ti,musb-dm816G@G@ =mccontrol��mc�host��$ �usb2-phy�� �h\%%%%%%%%%% % % % % %%%%%%%%%%% % % % % %�arx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15�default�&usb@47401800ti,musb-dm816G@G@ =mccontrol��mc�host��' �usb2-phy�� �h\%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%�arx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15�default�(dma-controller@47402000ti,am3359-cppi41 G@G@ G@0G@@@#=gluecontrollerschedulerqueuemgr��glue�)*7��%wd_timer@480c2000 ti,omap3-wdt �wd_timerH �memory@80000000smemory�@�@fixedregulator0regulator-fixed Evmmcsd_fixedT2Z�l2Z�� fixedclock0 fixed-clock�e��� compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1serial0serial1serial2ethernet0ethernet1device_typereginterruptsti,hwmodsranges#clock-cellsclocksphandleti,bit-shiftti,max-divti,dividers#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsreg-namesclock-names#phy-cellssysconclock-frequencyclock-indicesclock-output-namesinterrupt-namesdma-requests#dma-cellsti,tptcsti,edma-memcpy-channelsti,sysc-maskti,sysc-midleti,sysc-sidleti,gpio-always-ongpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsdmasdma-namesgpmc,num-csgpmc,num-waitpinspinctrl-namespinctrl-0linux,mtd-namerb-gpiosti,nand-ecc-optti,elm-idnand-bus-widthgpmc,device-widthgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,clk-activation-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabel#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rx#hwlock-cellsbus_freqti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizephy-handleti,spi-num-csspi-max-frequencyvmmc-supplycd-gpioswp-gpiosti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-pwmdr_modeinterface-typephysphy-namesmentor,multipointmentor,num-epsmentor,ram-bitsmentor,power#dma-channels#dma-requestsregulator-nameregulator-min-microvoltregulator-max-microvolt