� ��7083�(83�)STMicroelectronics STM32F769-DISCO board !st,stm32f769-discost,stm32f769interrupt-controller@e000e100!arm,armv7m-nvic,AR�� Vtimer@e000e010!arm,armv7m-systickR��^okay esoc !simple-busl}timers@40000000!st,stm32-timersR@ e��int ^disabledpwm !st,stm32-pwm� ^disabledtimer@1!st,stm32-timer-triggerR ^disabledtimers@40000400!st,stm32-timersR@ e��int ^disabledpwm !st,stm32-pwm� ^disabledtimer@2!st,stm32-timer-triggerR ^disabledtimers@40000800!st,stm32-timersR@ e��int ^disabledpwm !st,stm32-pwm� ^disabledtimer@3!st,stm32-timer-triggerR ^disabledtimers@40000c00!st,stm32-timerR@  e�^okay�2timers@40001000!st,stm32-timersR@ e��int ^disabledtimer@5!st,stm32-timer-triggerR ^disabledtimers@40001400!st,stm32-timersR@ e��int ^disabledtimer@6!st,stm32-timer-triggerR ^disabledtimers@40001800!st,stm32-timersR@ e��int ^disabledpwm !st,stm32-pwm� ^disabledtimer@11!st,stm32-timer-triggerR  ^disabledtimers@40001c00!st,stm32-timersR@ e��int ^disabledpwm !st,stm32-pwm� ^disabledtimers@40002000!st,stm32-timersR@  e��int ^disabledpwm !st,stm32-pwm� ^disabledrtc@40002800 !st,stm32-rtcR@( e � �l� �^okayserial@40004400!st,stm32f7-uartR@D�& e ^disabledserial@40004800!st,stm32f7-uartR@H�' e ^disabledserial@40004c00!st,stm32f7-uartR@L�4 e ^disabledserial@40005000!st,stm32f7-uartR@P�5 e ^disabledi2c@40005400!st,stm32f7-i2cR@T� � e^okay��default�� i2c@40005800!st,stm32f7-i2cR@X�!"� e ^disabledi2c@40005c00!st,stm32f7-i2cR@\�HI� e ^disabledi2c@40006000!st,stm32f7-i2cR@`�_`� e ^disabledcec@40006c00 !st,stm32-cecR@l�^e� �cechdmi-cec^okay��defaultserial@40007800!st,stm32f7-uartR@x�R e ^disabledserial@40007c00!st,stm32f7-uartR@|�S e ^disabledtimers@40010000!st,stm32-timersR@ e��int ^disabledpwm !st,stm32-pwm� ^disabledtimer@0!st,stm32-timer-triggerR ^disabledtimers@40010400!st,stm32-timersR@ e��int ^disabledpwm !st,stm32-pwm� ^disabledtimer@7!st,stm32-timer-triggerR ^disabledserial@40011000!st,stm32f7-uartR@�% e^okay��defaultserial@40011400!st,stm32f7-uartR@�G e ^disabledmmc@40011c00!arm,pl180arm,primecell%��R@ e� �apb_pclk�g<�l^okayJ V _�defaultopendrain� i smmc@40012c00!arm,pl180arm,primecell%��R@, e� �apb_pclk�1<�l ^disabledsyscon@40013800!st,stm32-syscfgsysconR@8Vinterrupt-controller@40013c00!st,stm32-exti,AR@<8� ()*>LVtimers@40014000!st,stm32-timersR@@ e��int ^disabledpwm !st,stm32-pwm� ^disabledtimer@8!st,stm32-timer-triggerR ^disabledtimers@40014400!st,stm32-timersR@D e��int ^disabledpwm !st,stm32-pwm� ^disabledtimers@40014800!st,stm32-timersR@H e��int ^disabledpwm !st,stm32-pwm� ^disabledpower-config@40007000!st,stm32-power-configsysconR@pVcrc@40023000!st,stm32f7-crcR@0 e  ^disabledrcc@40023800}�/!st,stm32f769-rccst,stm32f746-rccst,stm32-rccR@8e � ��B@Vdma-controller@40026000 !st,stm32-dmaR@` � / e� ^disableddma-controller@40026400 !st,stm32-dmaR@d �89:;<DEF e�� ^disabledusb@40040000!st,stm32f7-hsotgR@�M e�otg��  ���@@@@ ^okay�otg� �usb2-phy��defaultusb@50000000!st,stm32f4x9-fsotgRP�C e'�otg ^disabledpinctrl@40020000 }@0l� !st,stm32f769-pinctrlgpio@40020000+,AR e7GPIOAVgpio@40020400+,AR e7GPIOBgpio@40020800+,AR e7GPIOCgpio@40020c00+,AR  e7GPIODgpio@40021000+,AR e7GPIOEgpio@40021400+,AR e7GPIOFgpio@40021800+,AR e7GPIOGgpio@40021c00+,AR e7GPIOHgpio@40022000+,AR  e7GPIOIV gpio@40022400+,AR$ e 7GPIOJVgpio@40022800+,AR( e 7GPIOKcec-0VpinsDKUfusart1-0Vpins1D fsKpins2D fusart1-1pins1D fsKpins2Dfi2c1-0VpinsDfUKusbotg-hs-0Vpins0Dt �          fsKusbotg-hs-1pins0Dt "          fsKusbotg-fs-0pins D fsKsdio-pins-a-0pinsD( ) * + , 2 sKsdio-pins-od-a-0pins1D( ) * + , sKpins2D2 UKsdio-pins-b-0V pinsDi j   6 7 sKsdio-pins-od-b-0V pins1Di j   6 sKpins2D7 UKclocksclk-hse� !fixed-clock�}x@V clk-lse� !fixed-clock��clk-lsi� !fixed-clock�}clk-i2s-ckin� !fixed-clock��lV chosen�root=/dev/ram�serial0:115200n8memory@c0000000�memoryR�aliases�/soc/serial@40011000leds !gpio-ledsled-green Y �heartbeatled-red Y gpio-keys !gpio-keys�button-0�User�f Yusb-phy�!usb-nop-xceiv e �main_clkVmmc_vcard!regulator-fixed �mmc_vcard2Z� 2Z�V #address-cells#size-cellsmodelcompatibleinterrupt-controller#interrupt-cellsregphandlestatusclocksinterrupt-parentrangesclock-names#pwm-cellsinterruptsassigned-clocksassigned-clock-parentsst,syscfgresetspinctrl-0pinctrl-namesi2c-scl-rising-time-nsi2c-scl-falling-time-nsarm,primecell-periphidmax-frequencyvmmc-supplycd-gpiosbroken-cdpinctrl-1bus-width#reset-cells#clock-cellsassigned-clock-rates#dma-cellsst,mem2memg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modephysphy-namespins-are-numberedgpio-controller#gpio-cellsst,bank-namepinmuxslew-ratedrive-open-drainbias-disabledrive-push-pullclock-frequencybootargsstdout-pathdevice_typeserial0linux,default-triggerautorepeatlabellinux,code#phy-cellsregulator-nameregulator-min-microvoltregulator-max-microvolt