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SSSSS3�sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cguokay�defaultstate_uhs�T�U�� ���V�W�    + < V( e m smmc@11f70000(mediatek,mt8192-mmcmediatek,mt8183-mmc ���<g8�S SSSSS3�sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cguokay�defaultstate_uhs�X�Y�� �� ��Z�[ � � � e �gpu@13000000)mediatek,mt8192-maliarm,mali-valhall-jm�@0<mlk jobmmugpu�2(�77777 �core0core1core2core3core4 �\uokay �clock-controller@13fbf000mediatek,mt8192-mfgcfg����syscon@14000000mediatek,mt8192-mmsyssyscon��� �]] �]�mutex@14001000mediatek,mt8192-disp-mutex�<�� �] ���7 smi@14002000mediatek,mt8192-smi-common�  � �apbsmigals0gals1�7 �^larb@14003000mediatek,mt8192-smi-larb�0 # 4^��apbsmi�7 �blarb@14004000mediatek,mt8192-smi-larb�@ # 4^��apbsmi�7 �covl@14005000mediatek,mt8192-disp-ovl�P<�� A__�7  �]Povl@14006000mediatek,mt8192-disp-ovl-2l�`<��7 � A_"_  �]`rdma@140070004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdma�p<� A_ H�7  �]pcolor@140090006mediatek,mt8192-disp-colormediatek,mt8173-disp-color��<�7 � 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compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl-2l0ovl-2l2rdma0rdma4i2c0i2c1i2c2i2c3i2c7mmc0mmc1serial0#clock-cellsclocksclock-divclock-multclock-output-namesphandleclock-frequencydevice_typeregenable-methodcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domainscapacity-dmips-mhz#cooling-cellscpucache-levelcache-unifiedentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptsopp-sharedopp-hzopp-microvoltdma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxoutput-lowinput-enablebias-pull-updrive-strengthdrive-strength-microampbias-disablebias-pull-downoutput-high#power-domain-cellsclock-namesmediatek,infracfgdomain-supplyassigned-clocksassigned-clock-parentsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadregulator-compatible#mbox-cellsstatusresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsreset-names#pwm-cellspinctrl-namespinctrl-0mediatek,pad-selectspi-max-frequencywakeup-sourcegoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countlabelpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapcs-gpiosfirmware-namememory-regionmediatek,rpmsg-nameinterrupt-namesphysmediatek,syscon-wakeupvusb33-supplyvbus-supplymediatek,apmixedsysmediatek,topckgenpower-domainsbus-rangeinterrupt-map-maskinterrupt-mapnum-lanesspi-rx-bus-widthspi-tx-bus-widthenable-gpiosreset-gpiosvdd10-supplyvdd18-supplyvdd33-supplyremote-endpointpower-supplybacklightrealtek,jd-src#sound-dai-cellsAVDD-supplyDBVDD-supplyLDO1-IN-supplyMICVDD-supplyclock-stretch-nsvcc-supply#phy-cellspinctrl-1vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetmmc-hs400-enhanced-strobehs400-ds-delayno-sdiono-sdnon-removablecd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcpower-domain-namesoperating-points-v2mali-supplymboxesmediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusmediatek,rdma-fifo-sizephy-namesmediatek,larbs#iommu-cellsmediatek,scppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathpwmsbrightness-levelsnum-interpolated-stepsdefault-brightness-levelnum-channelswakeup-delay-msenable-active-highregulator-boot-ongpiovin-supplyoff-on-delay-usno-mapsdb-gpiosmediatek,platformpinctrl-2pinctrl-3pinctrl-4pinctrl-5pinctrl-6pinctrl-7pinctrl-8pinctrl-9pinctrl-10pinctrl-11pinctrl-12pinctrl-13pinctrl-14pinctrl-15pinctrl-16pinctrl-17pinctrl-18pinctrl-19pinctrl-20pinctrl-21pinctrl-22pinctrl-23pinctrl-24pinctrl-25sound-daifunctioncolormax-brightness