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�@qos@fe190300,rockchip,rk3568-qossyscon� �Aqos@fe190380,rockchip,rk3568-qossyscon�� �Bqos@fe190400,rockchip,rk3568-qossyscon� �Cqos@fe198000,rockchip,rk3568-qossyscon�� �;qos@fe1a8000,rockchip,rk3568-qossyscon�� �1qos@fe1a8080,rockchip,rk3568-qossyscon��� �2qos@fe1a8100,rockchip,rk3568-qossyscon�� �3dfi@fe230000,rockchip,rk3568-dfi�# � �apcie@fe260000,rockchip,rk3568-pcie0�@�&�[dbiapbconfig<�KJIHG�syspmcmsglegacyerr�( �����$ aclk_mstaclk_slvaclk_dbipclkaux�pci��`�bbbb���    pcie-phy7T��� � �@@V� pipe  �disabledlegacy-interrupt-controller�� �H�bmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc�+@ �b  ���� biuciuciu-driveciu-sample,7�рV� reset�okayEO *! 3�cdef�default >��mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc�,@ �c  ���� biuciuciu-driveciu-sample,7�рV� reset�okayEO *g  3�hijk�default >��spi@fe300000 ,rockchip,sfc�0@ �e xv clk_sfchclk_sfc�l�default �disabledmmc@fe310000,rockchip,rk3568-dwcmshc�1 �R{}b ��n6( |zy{} corebusaxiblocktimer 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�disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c�\ �1 LK  i2cpclk��default  �disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c�] �2 NM  i2cpclk���default  �disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c�^ �3 PO  i2cpclk���default �okay�^watchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt�` ��   tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spi�a �g RQ spiclkapb_pclk�'' Ltxrx�default ����  �disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spi�b �h TS spiclkapb_pclk�'' Ltxrx�default ����  �disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spi�c �i VU spiclkapb_pclk�'' Ltxrx�default ����  �disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spi�d �j XW spiclkapb_pclk�'' Ltxrx�default ����  �disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uart�e �u  baudclkapb_pclk�'' �����default���okay �bluetooth*,realtek,rtl8821cs-btrealtek,rtl8723bs-bt �Y �Y �Yserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uart�f �v #  baudclkapb_pclk�''���default�� �disabledserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uart�g �w '$ baudclkapb_pclk�''���default�� �disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uart�h �x +( baudclkapb_pclk�'' ���default�� �disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uart�i �y /, baudclkapb_pclk�' ' ���default�� �disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uart�j �z 30 baudclkapb_pclk�' ' ���default�� �disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uart�k �{ 74 baudclkapb_pclk�''���default�� �disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uart�l �| ;8 baudclkapb_pclk�''���default�� �disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uart�m �} ?< baudclkapb_pclk�''���default�� �disabledthermal-zonescpu-thermal �d �� ��tripscpu_alert0 p �?passive��cpu_alert1 $� �?passivecpu_crit s � ?criticalcooling-mapsmap0 �0 " �������� �������� �������� ��������gpu-thermal � �� ��tripsgpu-threshold p �?passivegpu-target $� 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�disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwm�p `_  pwmpclk���default� �disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwm�p `_  pwmpclk���default� �disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwm�p  `_  pwmpclk���default� �disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwm�p0 `_  pwmpclk���default� �disabledphy@fe830000,rockchip,rk3568-naneng-combphy�� "}  refapbpipeR"b��V� �� �� ��okay�phy@fe840000,rockchip,rk3568-naneng-combphy�� %~  refapbpipeR%b��V� �� �� � �disabled�phy@fe870000,rockchip,rk3568-csi-dphy�� y pclk �V� apb� �disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy��  refpclk z �7  apbV��okay�Tmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy��  refpclk { �7  apbV� �disabled�\usb2phy@fe8a0000,rockchip,rk3568-usb2phy��  phyclk�clk_usbphy0_480m �� ��+�okay�host-port � �disabledotg-port ��okay�usb2phy@fe8b0000,rockchip,rk3568-usb2phy��  phyclk�clk_usbphy1_480m �� ��+�okayhost-port ��okay�otg-port � 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�8button-left �� DPAD-LEFT �"button-r1 ��  TR �7button-r2 ��  TR2 �9button-right �� DPAD-RIGHT �#button-select �� SELECT �:button-start ��  START �;button-thumbl �� THUMBL �=button-thumbr �� THUMBR �>button-up �� DPAD-UP � button-x �� NORTH �3button-y �� WEST �4gpio-keys-vol ,gpio-keys ���defaultbutton-vol-down �� VOLUMEDOWN �rbutton-vol-up �� VOLUMEUP �smux-controller ,gpio-mux !! *��hdmi-con,hdmi-connector�^?cportendpointe��`pwm-leds ,pwm-ledsled-0 = Cstatus L� ��a�led-1 = Ccharging L� ��a�sdio-pwrseq,mmc-pwrseq-simple �  ext_clock���default [� Y�Hsound,simple-audio-card 8rk817_extOi2sh rHeadphoneHeadphones �HeadphonesHPOLHeadphonesHPORsimple-audio-card,codec��simple-audio-card,cpu��regulator-vcc3v3-lcd0,regulator-fixed �! ����default:L2Z�d2Z��vcc3v3_lcd0_n��Zregulator-state-mem�regulator-vcc-sys,regulator-fixed&:L9��d9���vcc_sys�$regulator-vcc-wifi,regulator-fixed � �!���default&:L2Z�d2Z� �vcc_wifi�L interrupt-parent#address-cells#size-cellscompatiblechassis-typemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc1mmc2mmc3device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendmonitored-batteryrockchip,resistor-sense-micro-ohmsrockchip,sleep-enter-current-microamprockchip,sleep-filter-current-microampfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablevmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointbacklightreset-gpiosvdd-supplyddc-i2c-busrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpsd-uhs-sdr104dma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsio-channelspoll-intervalabs-flatabs-fuzzabs-rangelinux,codeio-channel-namesmux-controlssettle-time-uspower-supplypwmscharge-full-design-microamp-hourscharge-term-current-microampconstant-charge-current-max-microampconstant-charge-voltage-max-microvoltfactory-internal-resistance-micro-ohmsvoltage-max-design-microvoltvoltage-min-design-microvoltocv-capacity-celsiusocv-capacity-table-0labelautorepeatmux-gpios#mux-control-cellscolorfunctionmax-brightnesspost-power-on-delay-mssimple-audio-card,widgetssimple-audio-card,routinggpioenable-active-high